(1) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a CMOS transistor having a self-aligned silicide (salicide) structure.
(2) Description of the Related Art
A method for fabricating a conventional CMOS transistor having a salicide structure of the kind to which the present invention relates is first explained to assist the understanding of the invention. As shown in FIGS. 1A-1D, an N well 302 is formed on a predetermined region of a surface of a P-type silicon substrate 301, and a field oxide film 304 and a gate oxide film 305 are respectively formed in an element isolation region and an element formation region. On an entire surface thereof is formed an N.sup.+ -type polycrystalline silicon film (not shown) which is patterned and, on the surface of the P-type silicon substrate 301 and the gate electrode formation region on the surface of the N well 302, the polycrystalline silicon film patterns 306aa and 306ab are respectively formed with the gate oxide film 305 interposed therebetween. Then, on the resulting entire surface, there is formed an insulating film of silicon oxide or silicon nitride having a predetermined thickness. This insulating film is etched back by anisotropic etching whereby an insulating film spacer 307 formed of the insulating film is formed at the sides of each of the polycrystalline silicon film patterns 306aa and 306ab (FIG. 1A).
Next, a high concentration N-type impurity is ion-implanted in a desired region including the element formation region on the surface of the P-type silicon substrate 301 using the polycrystalline silicon film pattern 306aa, the insulating film spacer 307, etc. as masks. Similarly, a high concentration P-type impurity is ion-implanted in a desired region including the element isolation formation region on the surface of the N well 302 using the polycrystalline silicon film pattern 306ab, the insulating film spacer 307, etc. as masks. Then, the resulting film is given a heat treatment such as a lamp annealing treatment, whereby an N.sup.+ -type diffusion layer 308 and P.sup.+ -type diffusion layer 309 are formed. Natural oxide films formed on surfaces of the polycrystalline silicon film pattern 306aa, the polycrystalline silicon film pattern 306ab, N.sup.+ -type diffusion layer 308 and the P.sup.+ -type diffusion layer 309 are removed, and the sputtering process provides the entire titanium film 322 having a predetermined thickness (FIG. 1B).
Then, because of a silicide chemical reaction through the Rapid Thermal Annealing (RTA) process in a nitrogen atmosphere at about 850.degree. C., a titanium/silicide film 324a is formed on surfaces of the polycrystalline silicon film pattern 306aa and the polycrystalline silicon film pattern 306ab, and a titanium/silicide film 324b is formed on surfaces of the N.sup.+ -type diffusion layer 308 and the P.sup.+ -type diffusion layer 309. Since this reaction does not occur on surfaces of the field oxide film 304, the insulating film spacer 307, etc., non-reacted titanium film 322a remains on these surfaces (FIG. 1C). Further, though it is not shown in the drawings, the titanium nitride film is formed on the surface of the titanium film 322a. The crystal structure of the titanium/silicide films 324a and 324b obtained by the RTA process under the above conditions is a C54 structure having a low resistive phase.
Next, the non-reacted titanium film 322a (and titanium nitride film) is selectively etched and removed by a mixed solution of ammonium (NH.sub.4 OH), hydrogen peroxide (H.sub.2 O.sub.2) and water. This results in the formation of a gate electrode 326aa formed of the polycrystalline silicon film pattern 306aa and the titanium/silicide film 324a, a gate electrode 326ab formed of the polycrystalline silicon film pattern 306ab and the titanium/silicide film 324a, an N.sup.+ -type source/drain region 328 formed of the N.sup.+ -type diffusion layer 308 and the titanium/silicide film 324b, and a P.sup.+ -type source/drain region 329 formed of the P.sup.+ -type diffusion layer 309 and the titanium/silicide film 324b, thus providing a CMOS transistor having a salicide structure (FIG. 1D).
In carrying out the above method for fabricating a CMOS transistor having a salicide structure, first there is a problem called "bridging phenomenon". As shown in FIGS. 2A and 2B which are sectional views for use in explaining the fabrication steps, as a result of a high temperature RTA treatment for obtaining a titanium/silicide film 324a, 324b having a C54 structure, a titanium/silicide film 324c is formed also on the insulating film spacer 307 (FIG. 2A). For example, on a surface of the insulating film spacer 307 formed at the sides of the polycrystalline silicon film pattern 306ab, the titanium/silicide film 324c is formed due to the diffusion into the titanium film from the polycrystalline silicon film 306ab and the P.sup.+ -type diffusion layer 309 during the RTA treat. This titanium/silicide film 324c normally does not cover the entire surface of the insulating film spacer 307 but are scattered on the surface thereof. Even after the non-reacted titanium film 322a (and titanium nitride film) has been removed, the titanium/silicide film 324c remains so that, for example, the leakage current between the gate electrode 326ab and the P.sup.+ -type source/drain region 329 is of a value that cannot be ignored, and in an extreme case, a short-circuiting is caused to occur (FIG. 2B).
For suppressing the bridging phenomenon explained above as one of the objects, there is a proposal wherein the RTA treatment is carried out in two stages. This proposal is disclosed by Ken-ichi Goto, et al under the title "Ti Salicide Process for Subquarter-Micron CMOS Devices" in IEICE Trans Electron Vol. E77-C, No. 3, pp. 480-485, March 1994. According to this proposal, the titanium film formed is subjected to a first RTA treatment in a nitrogen atmosphere at a temperature of 675.degree. C. for 30 seconds, the non-reacted titanium film (and titanium nitride film) is removed using a mixed solution of ammonium (NH.sub.4 OH), hydrogen peroxide (H.sub.2 O.sub.2) and water, and thereafter a second RTA treatment is carried out in a nitrogen atmosphere at a temperature of 800.degree. C. for 30 seconds. The first RTA treatment provides a titanium/silicide film having a C49 structure which is of a high resistive phase. Since this first RTA treatment is carried out at a comparatively low temperature, the rate of diffusion of the silicon into the titanium film is slow, and the bridging phenomenon does not readily occur. Also, since the film such as the non-reacted titanium film has been removed during the second RTA treatment which causes the phase transition to occur from the C49 structure to the C54 structure, the occurrence of the bridging phenomenon is unlikely.
However, in the method explained above, a problem is that the fabrication process takes a long time. Also, there are other problems (other than that of the bridging phenomenon) that are not solved by that method.
In the high temperature thermal treatment for obtaining the C54 structure, the titanium/silicide film formed by chemical reaction undergoes condensation so that there is a possibility for the layer resistivity to appear to be higher than the actual value. This phenomenon becomes more remarkable with a decrease in the thicknesses of the titanium film, and becomes also more remarkable with a decrease in the width (that is, the length of gate electrode) of the polycrystalline silicon film pattern. The decreasing of the thickness of the titanium film is to meet a need for making the junction depths respectively of the P.sup.+ -type diffusion layer and N.sup.+ -type diffusion layer as shallow as possible in order to miniaturize a semiconductor device.
For applying a salicide structure to a CMOS transistor, there are other kinds of factors, other than the condensation problem explained above, that prohibit the miniaturization. For example, when the titanium film is formed by a sputtering process and the thermal treatment is given at a temperature that provides the C54 structure, the thickness of the titanium/silicide film formed on a surface of the P.sup.+ -type diffusion layer (and P.sup.+ -type polycrystalline silicon film pattern) becomes thicker (about twice) than the thickness of the titanium/silicide film formed on a surface of the N.sup.+ -type diffusion layer (and N.sup.+ -type polycrystalline silicon film pattern). For this reason, it becomes necessary to increase the depth of the junction of the P.sup.+ -type diffusion layer, which prohibits the miniaturization of the CMOS transistor.